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publications
Assessing the Performance of Stateful Logic in 1-Selector-1-RRAM Crossbar Arrays
Published in 57th International Symposium on Circuits and Systems (ISCAS)
Resistive Random Access Memory (RRAM) crossbar arrays are an attractive memory structure for emerging nonvolatile memory due to their high density and excellent scalability. Their ability to perform logic operations using RRAM devices makes them a critical component in non-von Neumann processing-in-memory architectures. Passive RRAM crossbar arrays (1-RRAM or 1R), however, suffer from a major issue of sneak path currents, leading to a lower readout margin and increasing write failures. To address this challenge, active RRAM arrays have been proposed, which incorporate a selector device in each memory cell (termed 1-selector-1-RRAM or 1S1R). The selector eliminates currents from unselected cells and therefore effectively mitigates the sneak path phenomenon. Yet, there is a need for a comprehensive analysis of 1S1R arrays, particularly concerning in-memory computation. In this paper, we introduce a 1S1R model tailored to a VO2-based selector and TiN/TiOx/HfOx/Pt RRAM device. We also present simulations of 1S1R arrays, incorporating all parasitic parameters, across a range of array sizes from 4 × 4 to 512 × 512. We evaluate the performance of Memristor-Aided Logic (MAGIC) gates in terms of switching delay, power consumption, and readout margin, and provide a comparative evaluation with passive 1R arrays.
[Title Redacted]
Submitted to IEEE AICAS 2026
The unprecedented growth in the field of machine learning has led to the development of deep neuromorphic networks trained on labelled dataset with capability to mimic or even exceed human capabilities. However, for applications involving continuous decision making in unknown environments, such as rovers for space exploration, robots, unmanned aerial vehicles, etc., explicit supervision and generation of labelled data set is extremely difficult and expensive. Reinforcement learning (RL) allows the agents to take decisions without any (human/external) supervision or training on labelled dataset. However, the conventional implementations of RL on advanced digital CPUs/GPUs incur a significantly large power dissipation owing to their inherent von-Neumann architecture. Although crossbar arrays of emerging non-volatile memories such as resistive (R)RAMs with their innate capability to perform energy-efficient in situ multiply-accumulate operation appear promising for Q-learning-based RL implementations, their limited endurance restricts their application in practical RL systems with overwhelming weight updates. To address this issue and realize the true potential of RRAM-based RL implementations, in this work, for the first time, we perform an algorithm-hardware co-design and propose a novel implementation of Monte Carlo (MC) RL algorithm on passive RRAM crossbar array. We analyse the performance of the proposed MC RL implementation on the classical cart-pole problem and demonstrate that it not only outperforms the prior digital and active 1-Transistor-1-RRAM (1T1R)-based implementations by more than five orders of magnitude in terms of area but is also robust against the spatial and temporal variations and endurance failure of RRAMs.
[Title Redacted]
Submitted to IEEE/ACM DAC 2026
Several in-memory computing (IMC) works show how memory device interactions can be used to perform digital Boolean logic operations. Designing emerging memory architectures for digital IMC requires careful selection of both device-level and architecture-level properties such as device resistances, row/column voltages, execution control path, and inter-array organization. SPICE simulations, while accurate, are impractically slow and resource hungry when modeling digital IMC at architecture scale. As an alternative, we propose a rapid simulation methodology for digital IMC. Our approach avoids the need for complex equation solvers, and uses two novel techniques (variation-aware array memoization and state-aware dynamic time stepping) to enable runtime IMC modeling at the scale of an entire chip. We use real-world microbenchmarks to evaluate our simulator as it models transient behavior for a state-of-the-art chip-scale IMC system. Compared to an industrial SPICE-class tool (Cadence SpectreX) for our worst-case transient behavior, our simulator uses a tenth of the memory and delivers over 850X simulation speedup, with a mean error of 0.03%.
BRIE-RAM: Exploring Biodegradable Processing-Using-Memory for Sustainable Edge Sensing
Published in 2nd Workshop on Ethical Systems and Architecture Design (HotEthics)
Smart sensors at the edge have the potential to become ubiquitous, but for them to be effective, we must both (1) meet stringent energy constraints while processing increasingly large amounts of data, and (2) design devices that can sit for years in an environment or on organisms without contributing to e-waste. To address both concerns, we explore the feasibility of BRIE-RAM, which performs processing-using-memory inside biodegradable resistive RAM. We evaluate BRIE-RAM’s capabilities and shortcomings through a contemporary lens, and then discuss future research needs and ethical issues to tackle in order to bring BRIE-RAM to fruition.
talks
teaching
Teaching experience 1
Undergraduate course, University 1, Department, 2014
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Teaching experience 2
Workshop, University 1, Department, 2015
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